Memory systems may have memory installed on multiple memory buses attached to the memory chip. A memory rank is a logical unit of installable memory that may comprise of one or more Dual In-line Memory Modules (DIMMs). A high performance memory system is designed with ranks of memory installed on multiple independent buses. This arrangement increases the bandwidth (input/output capacity) because multiple ranks can be accessed simultaneously on independent buses.
One memory system comprises a memory interface that is split into mirror images, referred to as halves. In each mirror image half there is coherency logic that, in turn, controls two memory quadrants. For each quadrant (four in all) there is a scheduler that handles timing and which also controls the reads and writes. Each memory quadrant contains a memory buffer device (which may consist of multiple ASICs) that is accessed via a single high speed bus. The memory buffer device interfaces to two independent DRAM buses on which the ranks are installed. In the scheduler for each quadrant, there is a Memory Block Address Translation (MBAT) module, which translates addresses into the format used by the scheduler. As a set, the four MBAT modules define the quadrant, DRAM bus, and rank that a given address maps to, as well as supplying the bank, row, and column addresses recognized by the DRAM rank. Since installed ranks can consist of DIMMs constructed with DRAM parts of different densities, a rank can represent a variable amount of memory. When it is desired to install different size DIMMs in a system, a problem exists with mapping them into the address space so that there are no holes (ranges of unmapped addresses), and so that the logic supports the mapping of a set of addresses to a specified rank.
In order to optimize bandwidth, it is desired to map a set of addresses to each rank so that consecutive addresses map to ranks on different quadrants and DRAM buses. Prior to doing this, the ranks must be organized into groups (referred to as interleave groups) so that a range of addresses will map to an interleave group, with a set of addresses in the range mapping to each rank in the interleave group. For example, assume a range of addresses starting at address 0 are mapped to an interleave group. One of the ranks in that group represents ¼ of the memory in the group. The MBAT registers that correspond to that rank will be programmed such that every fourth address maps to that rank, starting with address 0, 1, 2, or 3. If the first address in the set is 0, the set will be (0,4,8, . . . ). If the first address is 1, the set will be (1,5,9, . . . ), etc. The address translation logic in the MBAT requires that the range of addresses that are mapped to an interleave group begins with an address on a power of 2 boundary that is a multiple of the size of the interleave group. It also requires that the set of addresses that map to each rank in the interleave group is constructed such that the difference between each pair of consecutive addresses in the set is the same, and is a power of two. In the previous example, it would not be possible to map the following set of addresses to the rank: (0,1,8,9,16,17, . . . ).
A problem exists with constructing a set of addresses for each rank such that all addresses in the range are mapped, and each address is mapped to a single rank. For example, assume an interleave group composed of three ranks that represent 1 gigabyte, 1 gigabyte, and 2 gigabytes of memory respectively. Suppose that the range of addresses from 0 to 4 gigabytes (0xffffffff) are mapped to the interleave group. Next suppose the set of addresses (0,4,8, . . . ) is mapped to the first 1 gigabyte rank, and the set of addresses (3,7,11, . . . ) is mapped to the second 1 gigabyte rank. All of the remaining addresses in the range must be mapped to the 2 gigabyte rank: (1,2,5,6, . . . ). This is not possible, because the difference between the first and second addresses in the set is not the same as the difference between the second and third addresses. The solution is to order the ranks in the interleave group from largest to smallest before assigning sets of addresses to each rank. In the previous example, the 2 gigabyte rank would be mapped first, to addresses (0,2,4, . . . ). One of the remaining 1 gigabyte ranks would be mapped to addresses (1,5,9, . . . ), and the remaining 1 gigabyte rank would be mapped to addresses (3,7,11, . . . ).
The problem of organizing ranks into interleave groups, and mapping a set of addresses to each rank, becomes more complicated as the number and size of possible ranks increases. For example, in a system having 32 ranks and perhaps six different possible memory sizes for each rank, there are numerous ways to organize the ranks into interleave groups and assign sets of addresses to each rank. A trial and error approach is time consuming and may not yield a result that optimizes bandwidth. A general method is desired which will work for any arbitrary number of ranks of varying sizes.
A prior art solution for grouping memories into interleaved groups and mapping them onto the address space was to specify a rule that only ranks of the same size could be placed in an interleave group. Then the interleave groups would be ordered according to the size of the memory they represented, with the largest interleave group being mapped to an address range starting with 0, the next largest interleave group being mapped to an address range starting where the first address range ended, and so on. In the example discussed above, there are ranks of two different sizes (1 and 2 gigabytes). Using the prior art solution, two interleave groups would be formed, one of them would contain the 2 gigabyte rank, and the other would contain the 1 gigabyte ranks. This configuration may result in non-optimal bandwidth because a set of consecutive addresses (0,1,2, . . . ) would be mapped to a single rank of 2 gigabytes instead of those consecutive addresses mapping to multiple ranks.
Another problem not formally addressed by the prior art solution is the assignment of ranks to an interleave group when there is a choice between two ranks of the same size, where one will be assigned to the interleave group, and the other will not. Assume that 6 ranks are installed in a system, each one representing 1 gigabyte of memory. Since an interleave group must be a power of two in size, two interleave groups will have to be formed. Four of the available ranks must be assigned to one of the interleave groups, and the remaining two ranks to the other. The assignment of the ranks may affect bandwidth. For example if four of the ranks are on a single DRAM bus, it would not be optimal to assign those four ranks to a single interleave group, because that would cause a large number of consecutive addresses to be directed to a single DRAM bus.